The present invention relates to a packet processing unit for performing a packet destination address process and the like in a router and the like.
Packet processing units have been used in a router and the like for performing packet destination address process and the like.
Conventionally, a packet processing unit provides methods of performing a packet destination address process, a solving process of Q o S information or an updating process of a packet header when required and the like through a software process.
But a rapid processing can not be implemented by the methods of performing the packet destination address process and the like through the software process.
Accordingly, a method implemented by a hardware configuration is considered for solving the above-mentioned problem.
However, in the event of implementing the destination address process through hardware, a plurality of lookup tables such as a Multi Field Classify table for performing a classification to identify packet flow by a multi field, a flow destination address table for performing forward with awareness of the flow and the like must be installed for processing a multi protocol or a multi layer. And a configuration providing circuits or tables only for performing each of the above-mentioned processes individually causes a problem of enlarged scale of a circuit.